X3T9.2/92-100 To: IDE (ATA) Committee Date: 4/13/92 From: Dave Smyth, INTEL, voice: (916) 351-5338, FAX: (916) 351-6710 Subject: IDE (ATA) document changes ---------------------------------------------------------------------------- I would like to request that the following changes be made to the current IDE (ATA) Rev. 3.0 document. The following information applies to figure 11-3 (DMA Data Transfer) of the Rev. 3.0 ATA IDE document. For document clarity, I recommend that the following changes be made: (1.1) DMACK#, DIOR#, DIOW# are active low signals. Your diagram shows these signals inverted. (2.1) DMREQ is an active high signal. Your diagram shows this signal inverted. (3.1) Timing tE (DIOR# data setup) should read DIOR# valid delay from DIOR# active. I would also like to request that the following changes and additions be made: (1.2) Timing tC (DIOR#/DIOW#) : This timing when generated by the source will probably be generated using either an 8.33Mhz or an 8.00Mhz BCLK. If an 8.33Mhz clock (120ns) is used, the current tC spec value of 120ns will be very hard to meet. If you account for rising and falling edge tracking differences (Approx. 5ns) and degradation of the signal by the time it gets to the IDE drive (Approx. 5ns) you are looking at a 120ns pulse turning into a 110ns pulse. I recommend that you change your tC (mode 2) spec to 110ns min, tC mode 1 spec to 230ns, and your tC mode 0 spec to 470ns. Timing (tC) Mode 0 Mode 1 Mode 2 (is) 480ns 240ns 120ns (should be) 470ns 230ns 110ns (2.2) Timing tE (DIOR# data setup/mode 2). If the pulse width spec is changed from 120ns to 110ns, as I have recommend above, read data setup at the receiving device would also be reduced. To make up for that reduction in setup time at the receiving device, I would change tE/mode 2 as indicated. Timing (tE) Mode 2 (is) 50ns (should be) 45ns (3.2) You should also include timings for DMA demand mode, with the following additions: (a) DMREQ valid delay from DIOR# or DIOW# (mode 2 = 40ns). This value will guarantee that you will meet EISA "B" type timings, and also make it easier to design a two BCLK Demand mode cycle (240ns). (b) DIOR# inactive pulse width (mode 2 = 45ns). This will guarantee that you will meet EISA "B" type timing. If you can not meet "B" type timings, you should try to meet 110ns min which would help when designing a two BCLK Demand mode cycle. (c) DIOW# inactive pulse width (mode 2 = 110ns). As stated in item 1.2 above, this should also be speced at 110ns for a 240ns demand mode cycle.